### quick and dirty sine generator

Type : sine generator
References : Posted by couriervst[AT]hotmail[DOT]com
Notes :
this is part of my library, although I've seen a lot of sine generators, I've never seen the simplest one, so I try to do it,
tell me something, I've try it and work so tell me something about it

Code :
PSPsample PSPsin1::doOsc(int numCh)
{

double x=0;
double t=0;

if(m_time[numCh]>m_sampleRate)    //re-init cycle
m_time[numCh]=0;

if(m_time[numCh]>0)
{
t =(double)(((double)m_time[numCh])/(double)m_sampleRate);

x=(m_2PI *(double)(t)*m_freq);
}
else
x=0;

PSPsample r=(PSPsample) sin(x+m_phase)*m_amp;

m_time[numCh]++;

return     r;

}

from : pete[AT]bannister25[DOT]plus[DOT]com
comment : isn't the sin() function a little bit heavyweight? Since this is based upon slices of time, would it not be much more processor efficient to use a state variable filter that is self oscillating? The operation: t =(double)(((double)m_time[numCh])/(double)m_sampleRate); also seems a little bit much, since t could be calculated by adding an interval value, which would eliminate the divide (needs more clocks). The divide would then only need to be done once. An FDIV may take 39 clock cycles minimum(depending on the operands), whilst an FADD is far faster (3 clocks). An FMUL is comparable to an add, which would be a predominant instruction if using the SVF method. FSIN may take between 16-126 clock cylces. (clock cycle info nabbed from: http://www.singlix.com/trdos/pentium.txt)

from : rossb[AT]audiomulch[DOT]com